With advancement of information technology, electronic product designs reveal a trend of light weight, thinness and compactness. Three dimensional integration techniques promote high density chip package in high efficiency and low power consumption. For instance, to the portable electronic devices with the characteristic of multi-function or small size, such as solid state drives (SSD) or DRAMs, processing performance thereof can be improved, and power consumption of chips during operation can be reduced without altering I/O terminals, so as to satisfy the demand of high capacity, high efficiency, and high density of I/O terminals.
The three dimensional chip integration techniques include the fabrication of through silicon via (TSV) and micro bumps, and steps of wafer thinning, alignment, bonding and dispensing. However, the existing bonding process, such as the chip-to-wafer (COW) bonding process, still suffers from some outstanding bottlenecks. For example, the high temperature of bonding process may cause high residual stress. Small scribe line in high density chip package is unfavorable for performing dispensing process. In addition, a molding process is conducted to a chip stack module following the dispensing process. However, after the molding process, since the chip stack module is provided by stacking a chip to a wafer temporarily attached to a carrier via an adhesive, part of the adhesive may not be completely removed and remain on bumps at the bottom of the wafer when debonding the wafer from the carrier, which affects processing yields. Furthermore, the bonding interface between the chip stack module and an external interposer or circuit substrate is fragile and affects the reliability of products.